1. Field of the Invention
This invention relates to a demodulated data recognition and decision device in which a signal modulated by digital data is demodulated and then the digital data is recovered from an obtained base band signal.
2. Description of the Prior Art
FIG. 1 is a block diagram for showing the conventional type of a demodulation data recognition and decision device (hereinafter called a decision device). In this figure, reference numeral 1 denotes an intermediate frequency signal (IF signal) output from an intermediate frequency circuit (not shown) of a previous stage. The detector and demodulation circuit 2 is for receiving the IF signal 1 and demodulating it into an output detection signal (a base band signal) 3. Comparator 4 is for converting the base band signal 3 to a binary value and outputting a binary signal 5. Clock recovery circuit 6 is for use in reproducing a clock signal 7 acting as the synchronous clock of a digital data stream 9 based on the binary signal 5, and 8 is a latch circuit for defining the digital data 9 from the binary signal 5 and the clock signal 7.
FIG. 2 is a timing diagram for indicating decision timing in the decision device shown in FIG. 1. In this figure, reference numeral 3 denotes the base signal 3 in FIG. 1 in a form of an eye pattern, and this wave-form is defined as a detection eye output. Reference numeral 10a denotes a decision timing and in this case this corresponds to the falling edge of the recovered clock signal 7 (in case of performing a data latching with the falling edge) and so reference symbol T corresponds to one symbol duration, i.e., the reciprocal of the symbol rate, of the digital data 9.
The operation of the prior art decision device will be described hereinafter. IF signal 1 is demodulated to the base band signal 3 acting as an analogue signal with the detection and demodulation circuit 2. This base band signal 3 is made as a binary value with a proper threshold value in the comparator 4. A binary signal 5 output by the comparator 4 is input into the latch circuit 8 and the clock recovered circuit 6. The clock recovery circuit 6 outputs the recovery clock signal 7 having the same rate as a bit rate of transmitted data on the basis of the binary signal 5. Since it is known that it is advantageous to sample the received waveform when the eye opening, as indicated in FIG. 2, is largest, it is preferable that the falling edge of the recovered clock signal 7 corresponds to the point in which the eye opening of the detected eye output 3 is the largest in size. Then, in the latch circuit 8, the input binary signal 5 is latched with the falling edge of the recovered clock signal 7 and output as a digital data 9.
Since the conventional type of decision device has been constructed as described above, problems have developed in that the timing in which the latch circuit 8 may latch the binary signal 5 is displaced from the point at which the eye opening is largest, and as a result, a margin of signal to noise is decreased which increases a rate of error. This displacement can result from the generation of a frequency or phase jitter of the base band signal 3 caused by the fading and/or the noise of a transmission line, i.e. in the case of generating a lateral jitter in the detected eye output 3. These errors can also result from the presence of an error in frequency or in phase of the recovered clock signal 7 or the like.